Table 11-11 Dwt Sleep Count Register Bit Assignments; Figure 11-9 Dwt Lsu Count Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

System Debug
Bits Field
[31:8] -
[7:0] SLEEPCNT
31
11-22
Table 11-11 describes the bit assignments of the DWT Sleep Count Register.
Function
Reserved.
Sleep counter. Counts the number of cycles during which the processor is sleeping. An event is
emitted on counter overflow (every 256 cycles). This counter initializes to 0 when enabled.
Note
SLEEPCNT is clocked using FCLK. It is possible that the frequency of FCLK might
be reduced while the processor is sleeping to minimize power consumption. This means
that sleep duration must be calculated with the frequency of FCLK during sleep.
DWT LSU Count Register
Use the DWT LSU Count Register to count the total number of cycles during which the
processor is processing an LSU operation beyond the first cycle.
The register address, access type, and Reset state are:
Address
0xE0001014
Access Read/write
Reset state -
Figure 11-9 describes the bit assignments of the DWT LSU Count Register.
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Table 11-11 DWT Sleep Count Register bit assignments

Reserved

Figure 11-9 DWT LSU Count Register bit assignments

Non-Confidential
8 7 0
LSUCNT
ARM DDI 0337G
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