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Bus Interface
14.5
External private peripheral interface
14-8
The external private peripheral interface is an Advanced Peripheral Bus (APB) (AMBA
v2.0) bus. Data and debug accesses to the External Peripheral memory space
(
0xE0040000 - 0xE00FFFFF
this bus. The TPIU and any vendor specific components populate this bus. Core data
accesses have higher priority than debug accesses, so debug accesses are waited until
core accesses have completed when there are simultaneous core and debug access to this
bus. Only the address bits necessary to decode the External PPB space are supported on
this interface. These address bits are bits [19:2] of PADDR.
PADDR31 is driven as a sideband signal on this bus. When the signal is HIGH, it
indicates that the AHB-AP debug is the requesting master. When the signal is LOW, it
indicates that the core is the requesting master.
Unaligned accesses to this bus are architecturally unpredictable and not supported. The
processor drives out the original HADDR[1:0] request from the core and does not
convert the request into multiple aligned accesses.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
) are performed over this bus. Wait states are not supported on
ARM DDI 0337B
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