Motorola PowerQUICC II MPC8280 Series Reference Manual page 221

Table 4-14 describes SYPCR fields.
Bits Name
0–15 SWTC Software watchdog timer count. Contains the count value for the software watchdog timer.
16–23 BMT Bus monitor timing. Defines the time-out period for the bus monitor, the granularity of this field is 8
bus clocks. (BMT = 0xFF is translated to 0x7f8 clock cycles). BMT is used both in the 60x and local
bus monitors.
Note that the value 0 in invalid; an error is generated for each bus transaction.
24 PBME 60x bus monitor enable.
0 60x bus monitor is disabled.
1 The 60x bus monitor is enabled.
25 LBME Local bus monitor enable.
0 Local bus monitor is disabled.
1 The local bus monitor is enabled.
26–28 — Reserved, should be cleared.
29 SWE Software watchdog enable. Enables the operation of the software watchdog timer. It should be
cleared by software after a system reset to disable the software watchdog timer.
30 SWRI Software watchdog reset/interrupt select.
0 Software watchdog timer and bus monitor time-out cause a machine check interrupt to the core.
1 Software watchdog timer and bus monitor time-out cause a hard reset (this is the default value
after soft reset).
31 SWP Software watchdog prescale. Controls the divide-by-2,048 software watchdog timer prescaler.
0 The software watchdog timer is not prescaled.
1 The software watchdog timer clock is prescaled.
4.3.2.9 Software Service Register (SWSR)
The software service register (SWSR) is the location to which the software watchdog timer
servicing sequence is written. To prevent software watchdog timer time-out, the user should
write 0x556C followed by 0xAA39 to this register, which resides at 0x1000E. SWSR can
be written at any time, but returns all zeros when read.
MOTOROLA
Freescale Semiconductor, Inc.
Table 4-14. SYPCR Field Descriptions
Chapter 4. System Interface Unit (SIU)
For More Information On This Product,
Go to: www.freescale.com
Description
Programming Model
4-39