Motorola PowerQUICC II MPC8280 Series Reference Manual page 208

Programming Model
INTR: • • •
Save state
R3 <- @ SIVEC
R4 <-- BASE OF BRANCH TABLE
• • •
lbz RX, R3 (0)
add RX, RX, R4
mtspr CTR, RX
bctr
BASE
BASE + 4
BASE + 8
BASE + C
BASE +10
BASE + n
Figure 4-19. Interrupt Table Handling Example
The
implementations in that when an interrupt request occurs,
SIVEC can be read. If there are multiple interrupt sources,
SIVEC latches the highest priority interrupt. Note that the
value of SIVEC cannot change while it is being read.
4.3.1.7 SIU External Interrupt Control Register (SIEXR)
Each defined bit in the SIU external interrupt control register (SIEXR), shown in
Figure 4-20, determines whether the corresponding port C line asserts an interrupt request
upon either a high-to-low change or any change on the pin. External interrupts can come
from port C (PC[0-15]).
4-26
Freescale Semiconductor, Inc.
# load as byte
b Routine1
b Routine2
b Routine3
b Routine4
•
•
NOTE
MPC8280 differs
MPC8280 PowerQUICC II Family Reference Manual
For More Information On This Product,
Go to: www.freescale.com
INTR: • • •
Save state
R3 <- @ SIVEC
R4 <-- BASE OF BRANCH TABLE
• • •
lhz RX, R3 (0)
add RX, RX, R4
mtspr CTR, RX
bctr
1st Instruction of Routine1
BASE
1st Instruction of Routine2
BASE + 400
BASE + 800 1st Instruction of Routine3
BASE + C00 1st Instruction of Routine4
BASE +1000
BASE + n
from previous MPC8xx
# load as half
•
•
•
•
•
•
•
•
MOTOROLA