Motorola PowerQUICC II MPC8280 Series Reference Manual page 225

4.3.2.12 Local Bus Transfer Error Status and Control Register 1
(L_TESCR1)
The local bus transfer error status and control register 1 (L_TESCR1) is shown in
Figure 4-33.
0 1 2
Field BM — PAR
Reset
R/W
Addr
16 17 18
Field — DMD —
Reset
R/W
Addr
Note: Bits 0–15 and 19–23 are status bits and are cleared by writing 1s.
Figure 4-33. Local Bus Transfer Error Status and Control Register 1 (L_TESCR1)
The L_TESCR1 register bits are described in Table 4-17.
Bits Name
0 BM Bus monitor time-out. Indicates that TEA was asserted due to the local bus monitor time-out.
1 — Reserved, should be cleared.
2 PAR Parity error. Indicates that MCP was asserted due to parity error on the local bus. L_TESCR2[PB]
indicates the byte lane that caused the error and L_TESCR2[BNK] indicates which memory
controller bank was accessed.
3–4 — Reserved, should be cleared.
5 WP Write protect error. Indicates that a write was attempted to a local bus memory region that was
defined as read-only in the memory controller. Note that this alone does not cause TEA assertion.
Usually, in this case, the bus monitor will time-out.
6 — Reserved, should be cleared.
7–9 TC Transfer code. Indicates the transfer code of the local bus transaction that caused the TEA.
000 60x-local bridge
001 Reserved
010 Local DMA function code 0
011 Local DMA function code 1
1xx Reserved
10 — Reserved, should be cleared.
11–15 TT Transfer type. Indicates the transfer type of the local bus transaction that caused the TEA.
Section 8.4.3.1, "Transfer Type Signal (TT[0–4]) Encoding," describes the various transfer types.
MOTOROLA
Freescale Semiconductor, Inc.
3 4 5 6
— WP —
0000_0000_0000_0000
19 20 21
DER
0000_0000_0000_0000
Table 4-17. L_TESCR1 Field Descriptions
Chapter 4. System Interface Unit (SIU)
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7 9 10 11
TC —
R/W
0x10048
—
R/W
0x1004A
Description
Programming Model
15
TT
31
4-43