Motorola PowerQUICC II MPC8280 Series Reference Manual page 219

Table 4-12. SIUMCR Register Field Descriptions (continued)
Bits Name
20 DBA Data output buffer impedance configuration. The pins in this group include D[0-63] and
PWE[0-7]/PSDDQM[0-7]/PBS[0-7].
0 The output buffer typical impedance is 45 Ω.
1 The output buffer typical impedance is 25 Ω.
21 ABA Address output buffer impedance configuration. The pins in this group include A[0-31],
PSDA10/PGPL0, PSDWE/PGPL1, POE/PSDRAS/PGPL2, PSDCAS/PGPL3, PGTA/PUPM,
WAIT/PGPl4, PSDAMUX/PGPL5 and BNKSEL[0:2].
0 The output buffer typical impedance is 45 Ω.
1 The output buffer typical impedance is 25 Ω.
22–31 — Reserved, should be cleared.
4.3.2.7 Internal Memory Map Register (IMMR)
The internal memory map register (IMMR), shown in Figure 4-29, contains identification
of a specific device as well as the base address for the internal memory map. Software can
deduce availability and location of any on-chip system resources from the values in IMMR.
PARTNUM and MASKNUM are mask programmed and cannot be changed for any
particular device.
0
Field
Reset Depends on reset configuration sequence. See Section 5.4.1, "Hard Reset Configuration Word."
R/W
Addr
16
Field
Reset
R/W
Addr
Figure 4-29. Internal Memory Map Register (IMMR)
MOTOROLA
Freescale Semiconductor, Inc.
ISB
PARTNUM
0000_1010
Chapter 4. System Interface Unit (SIU)
For More Information On This Product,
Go to: www.freescale.com
Description
R/W
0x101A8
23 24
MASKNUM
0000_0000
R
0x101AA
Programming Model
13 14 15
—
31
4-37