Motorola PowerQUICC II MPC8280 Series Reference Manual page 242

Reset Configuration
configuration master's A0 output latches the word driven on D[0–31] as its configuration
word. In this way the configuration master continues to configure all MPC8280 chips in the
system. The configuration master always reads eight configuration words regardless of the
number of MPC8280 parts in the system. In a simple system that uses one stand-alone
MPC8280, it is possible to use the default hard reset configuration word (all zeros). This is
done by tying RSTCONF input to VCC. Another scenario may be a system which has no
boot EPROM. In this case the user can configure the MPC8280 as a configuration slave by
driving RSTCONF to 1 during PORESET assertion and then applying a negative pulse on
RSTCONF and an appropriate configuration word on D[0–31]. In such a system, asserting
HRESET in the middle of operation causes the MPC8280 to return to the configuration
programmed after PORESET assertion (not the default configuration represented by
configuration word of all zeros).
5.4.1 Hard Reset Configuration Word
The contents of the hard reset configuration word are shown in Figure 5-4.
0 1 2
Field EARB EXMC CDIS EBM
Reset
16 17 18
Field BMS BBD MMR
Reset
Table 5-7 describes hard reset configuration word fields.
Table 5-7. Hard Reset Configuration Word Field Descriptions
Bits Name
1
0 EARB External arbitration. Defines the initial value for ACR[EARB]. If EARB = 1, external arbitration is
assumed. See Section 4.3.2.2, "60x Bus Arbiter Configuration Register (PPC_ACR)."
1 EXMC External MEMC. Defines the initial value of BR0[EMEMC]. If EXMC = 1, an external memory
controller is assumed. See Section 11.3.1, "Base Registers (BRx)."
1
2 CDIS Core disable. Defines the initial value for the SIUMCR[CDIS].
0 The core is active. See Section 4.3.2.6, "SIU Module Configuration Register (SIUMCR)."
1 The core is disabled. In this mode the MPC8280 functions as a slave.
1
3 EBM External bus mode. Defines the initial value of BCR[EBM]. See Section 4.3.2.1, "Bus
Configuration Register (BCR)."
4–5 BPS Boot port size. Defines the initial value of BR0[PS], the port size for memory controller bank 0.
00 64-bit port size
01 8-bit port size
10 16-bit port size
11 32-bit port size
See Section 11.3.1, "Base Registers (BRx)."
5-8
Freescale Semiconductor, Inc.
3 4 5 6
BPS CIP
0000_0000_0000_0000
19 20 21 22
LBPC APPC
0000_0000_0000_0000
Figure 5-4. Hard Reset Configuration Word
MPC8280 PowerQUICC II Family Reference Manual
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7 8 9 10
ISPS L2CPC DPPC
23 24 25 26
CS10PC ALD_EN
Description
11 12 13 15
PLLBP ISB
27 28 31
— MODCK_H
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