Motorola PowerQUICC II MPC8280 Series Reference Manual page 238

Reset Status Register (RSR)
clock cycles, after which the chip releases SRESET and exits the SRESET flow. An
external pull-up resistor should negate SRESET; after negation is detected, a 16-cycle
period is taken before testing the presence of an external (hard/soft) reset. While SRESET
is asserted, internal hardware is reset but hard reset configuration does not change.
5.2 Reset Status Register (RSR)
The reset status register (RSR), shown in Figure 5-2, is memory-mapped into the
MPC8280's SIU register map.
0
Field
R/W
Reset
Addr
16
Field
R/W
Reset
Addr
Table 5-3 describes RSR fields.
Bits Name
0–25 — Reserved, should be cleared.
26 JTRS JTAG reset status. When the JTAG reset request is set, JTRS is set and remains set until software
clears it. JTRS is cleared by writing a 1 to it (writing zero has no effect).
0 No JTAG reset event occurred
1 A JTAG reset event occurred
27 CSRS Check stop reset status. When the core enters a checkstop state and the checkstop reset is enabled
by the RMR[CSRE], CSRS is set and it remains set until software clears it. CSRS is cleared by
writing a 1 to it (writing zero has no effect).
0 No enabled checkstop reset event occurred
1 An enabled checkstop reset event occurred
28 SWRS Software watchdog reset status. When a software watchdog expire event (which causes a reset) is
detected, the SWRS bit is set and remains that way until the software clears it. SWRS is cleared by
writing a 1 to it (writing zero has no effect).
0 No software watchdog reset event occurred
1 A software watchdog reset event has occurred
5-4
Freescale Semiconductor, Inc.
0000_0000_0000_0000
—
0000_0000_0000_0011
Figure 5-2. Reset Status Register (RSR)
Table 5-3. RSR Field Descriptions
MPC8280 PowerQUICC II Family Reference Manual
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Go to: www.freescale.com
—
R/W
0x10C90
25 26 27
JTRS CSRS SWRS
R/W
0x10C92
Function
15
28 29 30 31
BMRS ESRS EHRS
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