Motorola PowerQUICC II MPC8280 Series Reference Manual page 215

Table 4-11 describes LCL_ACR register bits.
Bits Name
0–1 — Reserved, should be cleared.
2 DBGD Data bus grant delay. Specifies the minimum number of data tenure wait states for PowerPC
master-initiated data operations. This is the minimum delay between TS and DBG.
0 DBG is asserted with TS if the data bus is free.
1 DBG is asserted one cycle after TS if the data bus is not busy.
See Section 8.5.1, "Data Bus Arbitration."
3 — Reserved, should be cleared.
4–7 PRKM Parking master. Defines the parked master.
0000 CPM high request level refers to the IDMA which involves peripherals and the following serial
channels (SCC, SPI, SMC, and I
0001 CPM middle request level refers to all other serial channels (FCCs and MCCs)
0010 CPM low request level: it is possible to change the request level for all FCCs and MCCs to low
priority when PPC_ACR[4–7] = 0010 and FCRx[1] = 1 (See Section 28.7.1, "FCC Function
Code Registers (FCRx)."
0011 Host bridge
Values 0100–1111 are reserved.
4.3.2.5 Local Bus Arbitration Level Registers (LCL_ALRH and
LCL_ACRL)
The local bus arbitration level registers (LCL_ALRH and LCL_ALRL), shown in
Figure 4-26 and Figure 4-27, define arbitration priority for local bus masters 0–7. Priority
field 0 has highest-priority. For information about the MPC8280 local bus master indexes
see LCL_ACR[PRKM] in Table 4-11.
0
Field Priority Field 0
Reset 0000
R/W
Addr
16
Field Priority Field 4
Reset 0011
R/W
Addr
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Freescale Semiconductor, Inc.
Table 4-11. LCL_ACR Field Descriptions
2
C)
3 4
Priority Field 1
0001
19 20
Priority Field 5
0100
Figure 4-26. LCL_ALRH
Chapter 4. System Interface Unit (SIU)
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Description
7 8 11
Priority Field 2
0010
R/W
0x10038
23 24 27
Priority Field 6
0101
R/W
0x10040
Programming Model
12 15
Priority Field 3
0110
28 31
Priority Field 7
0111
4-33