Motorola PowerQUICC II MPC8280 Series Reference Manual page 224

Programming Model
4.3.2.11 60x Bus Transfer Error Status and Control Register 2
(TESCR2)
The 60x bus transfer error status and control register 2 (TESCR2) is shown in Figure 4-32.
0 1 2
Field — REGS DPR
Reset
R/W
Addr
16
Field
Reset
R/W
Addr
Note: all bits are status bits and are cleared by writing 1s.
Figure 4-32. 60x Bus Transfer Error Status and Control Register 2 (TESCR2)
The TESCR2 register is described in Table 4-16.
Bits Name
0 — Reserved, should be cleared.
1 REGS Internal registers error. An error occurred in a transaction to the MPC8280's internal registers.
2 DPR Dual port ram error. An error occurred in a transaction to the MPC8280's dual-port RAM.
3 — Reserved, should be cleared.
4 PCI0 PCI memory space 0 error. An error occurred in a transaction to the PCI memory space configured
by PCIBR0 and PCIMSK0.
5 PCI1 PCI memory space 1 error. An error occurred in a transaction to the PCI memory space configured
by PCIBR1 and PCIMSK1.
6 — Reserved, should be cleared.
7 LCL Local bus bridge error. An error occurred in a transaction to the MPC8280's 60x bus to local bus
bridge.
8–15 PB Parity error on byte. There are eight parity error status bits, one per 8-bit lane. A bit is set for the byte
that had a parity error.
16–27 BNK Memory controller bank. There are twelve error status bits, one per memory controller bank. A bit is
set for the 60x bus memory controller bank that had an error. Note that this field is invalid if the error
was not caused by ECC or parity checks.
28–31 — Reserved, should be cleared.
4-42
Freescale Semiconductor, Inc.
3 4 5 6
— PCI0 PCI1 —
0000_0000_0000_0000
BNK
0000_0000_0000_0000
Table 4-16. TESCR2 Field Descriptions
MPC8280 PowerQUICC II Family Reference Manual
For More Information On This Product,
Go to: www.freescale.com
7 8
LCL
R/W
0x10044
R/W
0x10046
Description
15
PB
27 28 31
—
MOTOROLA