Motorola PowerQUICC II MPC8280 Series Reference Manual page 209

0 1 2
Field EDPC0 EDPC1 EDPC2 EDPC3 EDPC4 EDPC5 EDPC6 EDPC7 EDPC8 EDPC9 EDPC
Reset
R/W
Addr
16 17 18
Field EDI0 EDI1 EDI2 EDI3 EDI4 EDI5 EDI6 EDI7
Reset
R/W
Addr
Figure 4-20. SIU External Interrupt Control Register (SIEXR)
Table 4-8 describes SIEXR fields.
Bits Name
0–15 EDPCx Edge detect mode for port Cx. The corresponding port C line (PCx) asserts an interrupt request
according to the following:
0 Any change on PCx generates an interrupt request.
1 High-to-low change on PCx generates an interrupt request.
16–23 EDIx Edge detect mode for IRQx. The corresponding IRQ line (IRQx) asserts an interrupt request
according to the following:
0 Low assertion on IRQx generates an interrupt request.
1 High-to-low change on IRQx generates an interrupt request.
4.3.2 System Configuration and Protection Registers
The system configuration and protection registers are described in the following sections.
4.3.2.1 Bus Configuration Register (BCR)
The bus configuration register (BCR), shown in Figure 4-21, contains configuration bits for
various features and wait states on the 60x bus.
MOTOROLA
Freescale Semiconductor, Inc.
3 4 5 6
0000_0000_0000_0000
0x10C24
19 20 21 22
0000_0000_0000_0000
R/W
0x10C26
Table 4-8. SIEXR Field Descriptions
Chapter 4. System Interface Unit (SIU)
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7 8 9 10
EDPC
10
R/W
23 24
Description
Programming Model
11 12 13 14 15
EDPC EDPC EDPC EDPC
11 12 13 14 15
31
—
R
4-27