Motorola PowerQUICC II MPC8280 Series Reference Manual page 172

Table 3-1. Internal Memory Map (continued)
Address
(offset)
0x11A48 SCC3 protocol-specific mode register (PSMR3)
0x11A4A Reserved
0x11A4C SCC3 transmit on demand register (TODR3)
0x11A4E SCC3 data synchronization register (DSR3)
0x11A50 SCC3 event register (SCCE3)
0x11A54 SCC3 mask register (SCCM3)
0x11A56 Reserved
0x11A57 SCC3 status register (SCCS3)
0x11A58– Reserved
0x11A5F
0x11A60 SCC4 general mode register (GSMR_L4)
0x11A64 SCC4 general mode register (GSMR_H4)
3-20
Freescale Semiconductor, Inc.
Register
SCC4
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R/W Size Reset
R/W 16 bits 0x0000
— 16 bits —
R/W 16 bits 0x0000
R/W 16 bits 0x7E7E
R/W 16 bits 0x0000
R/W 16 bits 0x0000
— 8 bits —
R/W 8 bits 0x00
— 8 bytes —
R/W 32 bits 0x0000_0000 20.1.1/-3
R/W 32 bits 0x0000_0000
Section/Page
20.1.2/-9
21.16/-14
(UART)
22.8/-7 (HDLC)
23.11/-10
(BISYNC)
24.9/-9
(Transparent)
25.17/-15
(Ethernet)
—
20.1.4/-10
20.1.3/-9
21.19/-20
(UART)
22.11/-13
(HDLC)
23.14/-15
(BISYNC)
24.12/-12
(Transparent)
25.20/-21
(Ethernet)
—
21.20/-22
(UART)
22.12/-15
(HDLC)
23.15/-16
(BISYNC)
24.13/-13
(Transparent)
—
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