Motorola PowerQUICC II MPC8280 Series Reference Manual page 175

Table 3-1. Internal Memory Map (continued)
Address
(offset)
0x11B20 SI1 TDMA1 mode register (SI1AMR)
0x11B22 SI1 TDMB1 mode register (SI1BMR)
0x11B24 SI1 TDMC1 mode register (SI1CMR)
0x11B26 SI1 TDMD1 mode register (SI1DMR)
0x11B28 SI1 global mode register (SI1GMR)
0x11B29 Reserved
0x11B2A SI1 command register (SI1CMDR)
0x11B2B Reserved
0x11B2C SI1 status register (SI1STR)
0x11B2D Reserved
0x11B2E SI1 RAM shadow address register (SI1RSR)
0x11B30 MCC1 event register (MCCE1)
0x11B32 Reserved
0x11B34 MCC1 mask register (MCCM1)
0x11B36 Reserved
0x11B38 MCC1 configuration register (MCCF1)
0x11B39– Reserved
0x11B3F
0x11B40 SI2 TDMA2 mode register (SI2AMR)
0x11B42 SI2 TDMB2 mode register (SI2BMR)
0x11B44 SI2 TDMC2 mode register (SI2CMR)
0x11B46 SI2 TDMD2 mode register (SI2DMR)
0x11B48 SI2 global mode register (SI2GMR)
0x11B49 Reserved
0x11B4A SI2 command register (SI2CMDR)
0x11B4B Reserved
0x11B4C SI2 status register (SI2STR)
0x11B4D Reserved
0x11B4E SI2 RAM shadow address register (SI2RSR)
MOTOROLA
Freescale Semiconductor, Inc.
Register
MCC1 Registers
1
1
1
SI2 Registers
MCC2 Registers
Chapter 3. Memory Map
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Go to: www.freescale.com
R/W Size Reset
R/W 16 bits 0x0000
R/W 16 bits 0x0000
R/W 16 bits 0x0000
R/W 16 bits 0x0000
R/W 8 bits 0x00
— 8 bits —
R/W 8 bits 0x00
— 8 bits —
R/W 8 bits 0x00
— 8 bits —
R/W 16 bits 0x0000
1
R/W 16 bits 0x0000
— 16 bits —
R/W 16 bits 0x0000
— 16 bits —
R/W 8 bits 0x00
— 7 bytes —
R/W 16 bits 0x0000
R/W 16 bits 0x0000
R/W 16 bits 0x0000
R/W 8 bits 0x0000
R/W 8 bits 0x00
— 8 bits —
R/W 8 bits 0x00
— 8 bits —
R/W 8 bits 0x00
— 16 bits —
R/W 16 bits 0x0000
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