Motorola PowerQUICC II MPC8280 Series Reference Manual page 190

Interrupt Controller
In Figure 4-7, the range is determined by SYPCR[SWTC]. The value in SWTC is then
loaded into a 16-bit decrementer clocked by the system clock. An additional
divide-by-2,048 prescaler is used when needed.
The decrementer begins counting when loaded with a value from SWTC. After the timer
reaches 0x0, a software watchdog expiration request is issued to the reset or MCP control
logic. Upon reset, SWTC is set to the maximum value and is again loaded into the software
watchdog register (SWR), starting the process over. When a new value is loaded into
SWTC, the software watchdog timer is not updated until the servicing sequence is written
to the SWSR. If SYPCR[SWE] is loaded with 0, the modulus counter does not count.
4.2 Interrupt Controller
Key features of the interrupt controller include the following:
• Communications processor module (CPM) interrupt sources (FCCs, SCCs, MCCs,
timers, SMCs, TC layers, I
• SIU interrupt sources (PIT, TMCNT, and PCI)
• 24 external sources (16 port C and 8 IRQ)
• Programmable priority between PIT, TMCNT, and PCI
• Programmable priority between SCCs, FCCs, and MCCs
• Two priority schemes for the SCCs: grouped, spread
• Programmable highest priority request
• Unique vector number for each interrupt source
4.2.1 Interrupt Configuration
Figure 4-8 shows the MPC8280 interrupt structure. The interrupt controller receives
interrupts from internal sources, such as the PIT or TMCNT, from the CPM, the PCI bridge
(with its own interrupt controller), and from external pins (port C parallel I/O pins).
4-8
Freescale Semiconductor, Inc.
2
C, IDMA, SDMA, and SPI)
MPC8280 PowerQUICC II Family Reference Manual
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