Motorola PowerQUICC II MPC8280 Series Reference Manual page 192

Interrupt Controller
The interrupt controller allows masking of each interrupt source. Multiple events within a
CPM sub-block event are also maskable.
All interrupt sources are prioritized and bits are set in the interrupt pending register
(SIPNR). On the MPC8280, the prioritization of the interrupt sources is flexible in the
following two aspects:
• The relative priority of the FCCs, SCCs, and MCCs can be modified
• One interrupt source can be assigned the highest priority
When an unmasked interrupt source is pending in the SIPNR, the interrupt controller sends
an interrupt request to the core. When an exception is taken, the interrupt mask bit in the
machine state register (MSR[EE]) is cleared to disable further interrupt requests until
software can handle them.
The SIU interrupt vector register (SIVEC) is updated with a 6-bit vector corresponding to
the sub-block with the highest current priority.
4.2.1.1 Machine Check Interrupt
There are several sources for a machine check interrupt (MCP):
• Software watchdog timer (when programmed to generate an interrupt—See
Section 4.1.5, "Software Watchdog Timer.")
• IRQ0 signal (when the internal core is enabled)
• Memory controller for parity/ECC errors (see Section 10.2.6, "Machine Check
Interrupt (MCP) Generation")
• PCI bridge
• Bus monitor time out (on an address only transaction—see Section 4.1.1, "Bus
Monitor")
When the internal core is enabled, these sources cause the interrupt controller to send a
MCP to the core. When the core is disabled the MCP assertion is reflected on
IRQ0/NMI_OUT so that an external core can serve it.
4.2.1.2 INT Interrupt
Besides the MCP sources listed above, all other interrupts are taken by the core through the
INT interrupt. If the internal core is disabled, INT is reflected on IRQ7/INT_OUT so that
an external core can serve it.
The interrupt controller allows masking of each interrupt source. Multiple events within a
CPM sub-block event are also maskable.
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MPC8280 PowerQUICC II Family Reference Manual
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