Motorola PowerQUICC II MPC8280 Series Reference Manual page 174

Table 3-1. Internal Memory Map (continued)
Address
(offset)
0x11A92 SMC2 mode register (SMCMR2)
0x11A94 Reserved
0x11A96 SMC2 event register (SMCE2)
0x11A97 Reserved
0x11A9A SMC2 mask register (SMCM2)
0x11A9B– Reserved
0x11A9F
0x11AA0 SPI mode register (SPMODE)
0x11AA2 Reserved
0x11AA6 SPI event register (SPIE)
0x11AA7 Reserved
0x11AAA SPI mask register (SPIM)
0x11AAB Reserved
0x11AAD SPI command register (SPCOM)
0x11AAE– Reserved
0x11AFF
0x11B00 CPM mux SI1 clock route register (CMXSI1CR)
0x11B02 CPM mux SI2 clock route register (CMXSI2CR)
0x11B03 Reserved
0x11B04 CPM mux FCC clock route register (CMXFCR)
0x11B08 CPM mux SCC clock route register (CMXSCR)
0x11B0C CPM mux SMC clock route register (CMXSMR)
0x11B0D Reserved
0x11B0E CPM mux UTOPIA address register (CMXUAR)
0x11B10– Reserved
0x11B1F
3-22
Freescale Semiconductor, Inc.
Register
SMC2
CPM Mux
SI1 Registers
MPC8280 PowerQUICC II Family Reference Manual
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R/W Size
R/W 16 bits
— 16 bits
R/W 8 bits
— 24 bits
R/W 8 bits
— 5 bytes
SPI
R/W 16 bits
— 4 bytes
R/W 8 bits
— 24 bits
R/W 8 bits
— 24 bits
W 8 bits
— 82 bytes
R/W 8 bits
R/W 8 bits
— 8 bits
R/W 32 bits
R/W 32 bits
R/W 8 bits
— 8 bits
2
R/W 16 bits
— 16 bytes
Reset Section/Page
0x0000 28.2.1/-3
— —
0x00 28.3.11/-20
(UART)
—
28.4.10/-31
(Transparent)
0x00
28.5.9/-37
(GCI)
— —
0x0000 39.4.1/-7
— —
0x00 39.4.2/-10
— —
0x00 39.4.2/-10
— —
0x00 39.4.3/-11
— —
0x00 16.4.2/-11
0x00 16.4.3/-12
— —
0x0000_0000 16.4.4/-13
0x0000_0000 16.4.5/-16
0x00 16.4.6/-19
— —
0x0000 16.4.1/-7
— —
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