Motorola PowerQUICC II MPC8280 Series Reference Manual page 186

System Configuration and Protection
4.1.1 Bus Monitor
The MPC8280 has two bus monitors, one for the 60x bus and one for the local bus. The bus
monitor ensures that each bus cycle is terminated within a reasonable period. The bus
monitor does not count when the bus is idle. When a transaction starts (TS asserted), the
bus monitor starts counting down from the time-out value. For standard bus transactions
with an address tenure and a data tenure, the bus monitor counts until a data beat is
acknowledged on the bus. It then reloads the time-out value and resumes the count down.
This process continues until the whole data tenure is completed. Following the data tenure
the bus monitor will idle in case there is no pending transaction; otherwise it will reload the
time-out value and resume counting.
For address-only transactions, the bus monitor counts until AACK is asserted. If the
monitor times out for a standard bus transaction, transfer error acknowledge (TEA) is
asserted. If the monitor times out for an address-only transaction, the bus monitor asserts
AACK and a core machine check or reset interrupt is generated, depending on
SYPCR[SWRI]. To allow variation in system peripheral response times, SYPCR[BMT]
defines the time-out period, whose maximum value can be 2,040 system bus clocks. The
timing mechanism is clocked by the system bus clock divided by eight.
4.1.2 Timers Clock
The two SIU timers (the time counter and the periodic interrupt timer) use the same clock
source, timersclk, which can be derived from several sources, as described in Figure 4-3.
The user should select external clock and/or BRG1 programming
to yield either 4 MHz or 32 KHz at this point.
PC[26]
CPM clock
PC[27]
PC[29]
Ports Programming
PC[25]
4-4
Freescale Semiconductor, Inc.
BRG1
Figure 4-3. Timers Clock Generation
MPC8280 PowerQUICC II Family Reference Manual
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Divide by 4
Divide by 512
Ports Programming
TMCNTSC[TCF]
PISCR[PTF]
timersclk for PIT
timersclk for TMCNT
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