Motorola PowerQUICC II MPC8280 Series Reference Manual page 207

4.3.1.6 SIU Interrupt Vector Register (SIVEC)
The SIU interrupt vector register (SIVEC), shown in Figure 4-18, contains an 8-bit code
representing the unmasked interrupt source of the highest priority level.
0
Field Interrupt Code
Reset
R/W
Addr
16 17 18
Field 0 0 0
Reset
R/W
Addr
Figure 4-18. SIU Interrupt Vector Register (SIVEC)
The SIVEC can be read as either a byte, half word, or a word. When read as a byte, a branch
table can be used in which each entry contains one instruction (branch). When read as a half
word, each entry can contain a full routine of up to 256 instructions. The interrupt code is
defined such that its two lsbs are zeroes, allowing indexing into the table, as shown in
Figure 4-19.
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Freescale Semiconductor, Inc.
5 6
0
0000_0000_0000_0000
19 20 21 22
0 0 0 0
0000_0000_0000_0000
Chapter 4. System Interface Unit (SIU)
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7 8 9 10 11
0 0 0 0 0
R
0x10C04
23 24 25 26 27
0 0 0 0 0
R
0x10C06
Programming Model
12 13 14 15
0 0 0 0
28 29 30 31
0 0 0 0
4-25