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Programming Model
Figure 4-16 shows the SIMR_H register.
0
1
2
Field PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12
Reset
R/W
Addr
16
17
18
Field
—
IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7
Reset
R/W
Addr
Figure 4-17 shows SIMR_L.
0
1
2
Field FCC1 FCC2 FCC3
Reset
R/W
Addr
16
17
18
Field I2C
SPI
RTT SMC1 SMC2 IDMA1 IDMA2 IDMA3 IDMA4 SDMA
Reset
R/W
Addr
2
MPC8280 only. Reserved on the other devices.
Note the following:
• SCC/TC/MCC/FCC SIMR bit positions are not affected by their relative priority.
• The user can clear pending register bits that were set by multiple interrupt events
only by clearing all unmasked events in the corresponding event register.
• If an SIMR bit is masked at the same time that the corresponding SIPNR bit causes
an interrupt request to the core, the error vector is issued (if no other interrupts
pending). Thus, the user should always include an error vector routine, even if it
contains only an rfi instruction. The error vector cannot be masked.
4-24
Freescale Semiconductor, Inc.
3
4
5
6
0000_0000_0000_0000
19
20
21
22
0000_0000_0000_0000
Figure 4-16. SIMR_H
3
4
5
6
1
—
MCC1
MCC2
—
0000_0000_0000_0000
19
20
21
22
0000_0000_0000_0000
Figure 4-17. SIMR_L
MPC8280 PowerQUICC II Family Reference Manual
For More Information On This Product,
Go to: www.freescale.com
7
8
9
10
11
R/W
0x10C1C
23
24
—
R/W
0x10C1E
7
8
9
10
SCC1 SCC2 SCC3 SCC4
R/W
0x10C20
23
24
25
26
—
R/W
0x10C22
12
13
14
PC13
PC14 PC15
28
29
30
TMCNT
PIT
PCI
11
12
13
1
TC
—
27
28
29
TIMER1 TIMER2 TIMER3 TIMER4 —
MOTOROLA
15
31
15
30
31
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