Motorola PowerQUICC II MPC8280 Series Reference Manual page 204

Programming Model
Table 4-7 describes SCPRR_L fields.
Bits Name
0–2 YC1P–YCC1 Priority order. Defines which SCC asserts its request in the YCC1 priority position. Do not
program the same SCC to multiple priority positions. This field can be changed dynamically.
000 SCC1 asserts its request in the YCC1 position.
001 SCC2 asserts its request in the YCC1 position.
010 SCC3 asserts its request in the YCC1 position.
011 SCC4 asserts its request in the YCC1 position.
100 TC layer asserts its request in the YCC1 position (MPC8280 only. Reserved on other
1XX YCC1 position is not active.
3–11 YC2P–YC8P Same as YC1P, but for YCC2–YCC8
12–15 — Reserved, should be cleared.
16–27 YC5P–YC8P Same as YC1P, but for YCC5–YCC8
28–31 — Reserved, should be cleared.
4.3.1.4 SIU Interrupt Pending Registers (SIPNR_H and SIPNR_L)
Each bit in the interrupt pending registers (SIPNR_H and SIPNR_L), shown in Figure 4-14
and Figure 4-15, corresponds to an interrupt source. When an interrupt is received, the
interrupt controller sets the corresponding SIPNR bit.
0 1 2
Field PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15
Reset
R/W
Addr
16 17 18
Field — IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7
Reset Undefined (the user should write 1s to clear these bits before using)
R/W
Addr
1
These fields are zero after reset because their corresponding mask register bits are cleared (disabled).
4-22
Freescale Semiconductor, Inc.
Table 4-7. SCPRR_L Field Descriptions
devices.)
3 4 5 6
Undefined (the user should write 1s to clear these bits before using)
19 20 21 22
Figure 4-14. SIPNR_H
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Description
7 8 9 10 11
R/W
0x10C08
23 24
—
R/W
0x10C10
12 13 14 15
28 29 30 31
TMCNT PIT PCI
1 1 1
0 0 0
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