Clearing Sleep Mode; Clock Frequency In Sleep (Medium-Speed) Mode - Renesas H8 Series Hardware Manual

5.2.2

Clearing Sleep Mode

Sleep mode is cleared by any interrupt (timer A, timer C, timer F, timer G, asynchronous event
counter, IRQAEC, IRQ
the pin.
R E S
• Clearing by interrupt
When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts.
A transition is made from sleep (high-speed) mode to active (high-speed) mode, or from sleep
(medium-speed) mode to active (medium-speed) mode. Sleep mode is not cleared if the I bit of
the condition code register (CCR) is set to 1 or the particular interrupt is disabled in the
interrupt enable register.
To synchronize the interrupt request signal with the system clock, up to 2/φ(s) delay may occur
after the interrupt request signal occurrence, before the interrupt exception handling start.
•
Clearing by
R E S
When the pin goes low, the CPU goes into the reset state and sleep mode is cleared.
R E S
5.2.3

Clock Frequency in Sleep (Medium-Speed) Mode

Operation in sleep (medium-speed) mode is clocked at the frequency designated by the MA1 and
MA0 bits in SYSCR1.
, IRQ , IRQ , IRQ
4 3 1 0
input
, WKP to WKP , SCI3, A/D converter), or by input at
7 0
Rev. 7.00 Mar 10, 2005 page 127 of 652
Section 5 Power-Down Modes
REJ09B0042-0700