Operating Frequency In Subactive Mode; Active (Medium-Speed) Mode; Transition To Active (Medium-Speed) Mode; Clearing Active (Medium-Speed) Mode - Renesas F-ZTAT H8 Series Hardware Manual

5. Power-Down Modes
5.6.3

Operating Frequency in Subactive Mode

The operating frequency in subactive mode is set in bits SA1 and SA0 in SYSCR2. The choices
are φ /2, φ /4, and φ
W W W
5.7

Active (medium-speed) Mode

5.7.1

Transition to Active (medium-speed) Mode

If the MSON bit in SYSCR2 is set to 1 while the LSON bit in SYSCR1 is cleared to 0, a transition
to active (medium-speed) mode results from IRQ
mode, timer A, IRQ , or WKP
0
A transition to active (medium-speed) mode does not take place if the I bit of CCR is set to 1 or
the particular interrupt is disabled in the interrupt enable register.
5.7.2

Clearing Active (medium-speed) Mode

Active (medium-speed) mode is cleared by a SLEEP instruction or by a input at the RES pin.
Clearing by SLEEP Instruction: A transition to standby mode takes place if a SLEEP
instruction is executed while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is
cleared to 0, and TMA3 bit in TMA is cleared to 0. The system goes to watch mode if the SSBY
bit in SYSCR1 is set to 1 and TMA3 bit in TMA is set to 1 when a SLEEP instruction is executed.
Sleep mode is entered if both SSBY and LSON are cleared to 0 when a SLEEP instruction is
executed. Direct transfer to active (high-speed) mode or to subactive mode is also possible. See
section 5.8, Direct Transfer, below for details.
Clearing by RES Pin: When the RES pin goes low, the CPU enters the reset state and active
(medium-speed) mode is cleared.
5.7.3

Operating Frequency in Active (medium-speed) Mode

In active (medium-speed) mode, the CPU is clocked at 1/8 the frequency in active (high-speed)
mode.
Rev.3.00 Jul. 19, 2007 page 114 of 532
REJ09B0397-0300
/8.
to WKP interrupts in watch mode, or any interrupt in sleep mode.
0 7
, IRQ , or WKP to WKP
0 1 0
interrupts in standby
7