Gpio Port Pull-Up/Pull-Down Register (Gpiox_Pupdr) (X = A..h; Gpio Port Input Data Register (Gpiox_Idr) (X = A..h - ST STM32F446 Series Reference Manual

Advanced arm-based 32-bit mcus
Hide thumbs Also See for STM32F446 Series:
Table of Contents

Advertisement

RM0390
7.4.4

GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A..H)

Address offset: 0x0C
Reset values:
0x6400 0000 for port A
0x0000 0100 for port B
0x0000 0000 for other ports
31
30
29
28
PUPDR15[1:0]
PUPDR14[1:0]
rw
rw
rw
rw
15
14
13
12
PUPDR7[1:0]
PUPDR6[1:0]
rw
rw
rw
rw
Bits 2y:2y+1 PUPDRy[1:0]: Port x configuration bits (y = 0..15)
7.4.5

GPIO port input data register (GPIOx_IDR) (x = A..H)

Address offset: 0x10
Reset value: 0x0000 XXXX (where X means undefined)
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
IDR15
IDR14
IDR13
IDR12
r
r
r
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 IDRy: Port input data (y = 0..15)
27
26
25
PUPDR13[1:0]
PUPDR12[1:0]
rw
rw
rw
11
10
9
PUPDR5[1:0]
PUPDR4[1:0]
rw
rw
rw
These bits are written by software to configure the I/O pull-up or pull-down
00: No pull-up, pull-down
01: Pull-up
10: Pull-down
11: Reserved
27
26
25
Res.
Res.
Res.
11
10
9
IDR11
IDR10
IDR9
r
r
r
r
These bits are read-only and can be accessed in word mode only. They contain the input
value of the corresponding I/O port.
24
23
22
PUPDR11[1:0]
PUPDR10[1:0]
rw
rw
rw
8
7
6
PUPDR3[1:0]
PUPDR2[1:0]
rw
rw
rw
24
23
22
Res.
Res.
Res.
Res.
8
7
6
IDR8
IDR7
IDR6
IDR5
r
r
r
RM0390 Rev 4
General-purpose I/Os (GPIO)
21
20
19
18
PUPDR9[1:0]
rw
rw
rw
rw
5
4
3
2
PUPDR1[1:0]
rw
rw
rw
rw
21
20
19
18
Res.
Res.
Res.
5
4
3
2
IDR4
IDR3
IDR2
r
r
r
r
17
16
PUPDR8[1:0]
rw
rw
1
0
PUPDR0[1:0]
rw
rw
17
16
Res.
Res.
1
0
IDR1
IDR0
r
r
189/1328
194

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the STM32F446 Series and is the answer not in the manual?

Questions and answers

Subscribe to Our Youtube Channel

This manual is also suitable for:

Rm0390

Table of Contents

Save PDF