Gpio Port Input Data Register (Gpiox_Idr); (X = A To F); Gpio Port Output Data Register (Gpiox_Odr); Gpio Port Bit Set/Reset Register (Gpiox_Bsrr) - ST STM32G0 1 Series Reference Manual

RM0444
7.4.5

GPIO port input data register (GPIOx_IDR)

(x = A to F)

Address offset: 0x10
Reset value: 0x0000 XXXX
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
ID15 ID14 ID13 ID12
r r r
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 ID[15:0]: Port x input data I/O pin y (y = 15 to 0)
7.4.6

GPIO port output data register (GPIOx_ODR)

(x = A to F)
Address offset: 0x14
Reset value: 0x0000 0000
31 30 29
Res. Res. Res.
15 14 13
OD15 OD14 OD13 OD12
rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 OD[15:0]: Port output data I/O pin y (y = 15 to 0)
These bits can be read and written by software.
Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the
7.4.7

GPIO port bit set/reset register (GPIOx_BSRR)

(x = A to F)
Address offset: 0x18
Reset value: 0x0000 0000
31 30 29
BR15 BR14 BR13 BR12
w w w
27 26 25
Res. Res. Res.
11 10 9
ID11 ID10 ID9
r r r r
These bits are read-only. They contain the input value of the corresponding I/O port.
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
OD11 OD10 OD9
rw rw rw rw
GPIOx_BSRR register (x = A..D, F).
28 27 26 25
BR11 BR10 BR9
w w w w
24 23 22
Res. Res. Res. Res.
8 7 6
ID8 ID7 ID6 ID5
r r r
24 23 22
Res. Res. Res.
8 7 6
OD8 OD7 OD6
rw rw rw
24 23 22
BR8 BR7 BR6
w w w
RM0444 Rev 5
General-purpose I/Os (GPIO)
21 20 19 18
Res. Res. Res.
5 4 3 2
ID4 ID3 ID2
r r r r
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
OD5 OD4 OD3 OD2
rw rw rw rw
21 20 19 18
BR5 BR4 BR3 BR2
w w w w
17 16
Res. Res.
1 0
ID1 ID0
r r
17 16
Res. Res.
1 0
OD1 OD0
rw rw
17 16
BR1 BR0
w w
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