Gpio Port Input Data Register (Gpiox_Idr) (X = A; Gpio Port Output Data Register (Gpiox_Odr) (X = A; Gpio Port Bit Set/Reset Register (Gpiox_Bsrr) (X = A - ST STM32F207 Series Reference Manual

RM0033
6.4.5 GPIO port input data register (GPIOx_IDR) (x = A..I)
Address offset: 0x10
Reset value: 0x0000 XXXX (where X means undefined)
31 30 29 28
15 14 13 12
IDR15 IDR14 IDR13 IDR12
r r r
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 IDRy: Port input data (y = 0..15)
6.4.6 GPIO port output data register (GPIOx_ODR) (x = A..I)
Address offset: 0x14
Reset value: 0x0000 0000
31 30 29
15 14 13
ODR15 ODR14 ODR13 ODR12 ODR11 ODR10
rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 ODRy: Port output data (y = 0..15)
Note: For atomic bit set/reset, the ODR bits can be individually set and reset by writing to the
6.4.7 GPIO port bit set/reset register (GPIOx_BSRR) (x = A..I)
Address offset: 0x18
Reset value: 0x0000 0000
31 30 29
BR15 BR14 BR13 BR12
w w w
15 14 13
BS15 BS14 BS13 BS12
w w w
27 26 25
11 10 9
IDR11 IDR10 IDR9
r r r r
These bits are read-only and can be accessed in word mode only. They contain the input
value of the corresponding I/O port.
28 27 26 25
12 11 10 9
ODR9
rw rw rw rw
These bits can be read and written by software.
GPIOx_BSRR register (x = A..I).
28 27 26 25
BR11 BR10 BR9
w w w w
12 11 10 9
BS11 BS10 BS9
w w w w
24 23 22
Reserved
8 7 6
IDR8 IDR7 IDR6 IDR5
r r r
24 23 22
Reserved
8 7 6
ODR8 ODR7 ODR6 ODR5
rw rw rw
24 23 22
BR8 BR7 BR6
w w w
8 7 6
BS8 BS7 BS6
w w w
RM0033 Rev 9
General-purpose I/Os (GPIO)
21 20 19 18
5 4 3 2
IDR4 IDR3 IDR2
r r r r
21 20 19 18
5 4 3 2
ODR4 ODR3 ODR2
rw rw rw rw
21 20 19 18
BR5 BR4 BR3 BR2
w w w w
5 4 3 2
BS5 BS4 BS3 BS2
w w w w
17 16
1 0
IDR1 IDR0
r r
17 16
1 0
ODR1 ODR0
rw rw
17 16
BR1 BR0
w w
1 0
BS1 BS0
w w
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