Rcc Backup Domain Control Register (Rcc_Bdcr) - ST STM32F412 Reference Manual

RM0402
6.3.20

RCC Backup domain control register (RCC_BDCR)

Address offset: 0x70
Reset value: 0x0000 0000, reset by Backup domain reset.
Access: 0
Wait states are inserted in case of successive accesses to this register.
The LSEON, LSEBYP, RTCSEL and RTCEN bits in the
register (RCC_BDCR)
write-protected and the DBP bit in the
(PWR_CR)
control/status register (PWR_CSR)
Backup domain Reset (see
Reset will not have any effect on these bits.
31 30 29
Res. Res. Res. Res.
15 14 13
RTCEN Res. Res. Res.
rw
Bits 31:17 Reserved, must be kept at reset value.
Bit 16 BDRST: Backup domain software reset
Set and cleared by software.
0: Reset not activated
1: Resets the entire Backup domain
Bit 15 RTCEN: RTC clock enable
Set and cleared by software.
0: RTC clock disabled
1: RTC clock enabled
Bits 14:10 Reserved, must be kept at reset value.
Bits 9:8 RTCSEL[1:0]: RTC clock source selection
Set by software to select the clock source for the RTC. Once the RTC clock source has been
selected, it cannot be changed anymore unless the Backup domain is reset. The BDRST bit
can be used to reset them.
00: No clock
01: LSE oscillator clock used as the RTC clock
10: LSI oscillator clock used as the RTC clock
11: HSE oscillator clock divided by a programmable prescaler (selection through the
RTCPRE[4:0] bits in the RCC clock configuration register (RCC_CFGR)) used as the RTC
clock
Bits 7:4 Reserved, must be kept at reset value.
Bit 3 LSEMOD: External low-speed oscillator bypass
Set and reset by software to select crystal mode for low speed oscillator. Two power modes
are available.
0: LSE oscillator "low power" mode selection
1: LSE oscillator "high drive" mode selection
wait state 3, word, half-word and byte access
≤ ≤
are in the Backup domain. As a result, after Reset, these bits are
has to be set before these can be modified. Refer to
Section 6.1.3: Backup domain
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. RTCSEL[1:0]
rw
Reset and clock control (RCC) for STM32F412xx
Section 5.4.1: PWR power control register
for further information. These bits are only reset after a
24 23 22 21
Res. Res. Res. Res.
8 7 6
Res. Res. Res.
rw
RM0402 Rev 6
RCC Backup domain control
Section 5.4.2: PWR power
reset). Any internal or external
20 19 18
Res. Res. Res.
5 4 3 2
Res. LSEMOD LSEBYP LSERDY LSEON
rw rw
17 16
Res. BDRST
rw
1 0
r rw
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