Rcc Backup Domain Control Register (Rcc_Bdcr) - ST STM32WL5 Series Reference Manual

RM0453
7.4.30

RCC Backup domain control register (RCC_BDCR)

Address offset: 0x090
Reset value: 0x0000 0000
Reset by Backup domain reset, except LSCOSEL, LSCOEN and BDRST that are reset only
by Backup domain power-on reset but not reset by wakeup from Standby and NRST pad.
Access: 0 ≤ wait state ≤ 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.
Note: The bits of this register are outside of the V
are write-protected and the DBP bit in the
before these bits can be modified. Refer to
information. These bits (except LSCOSEL, LSCOEN and BDRST) are only reset after a
Backup domain reset (see
reset has no effect on these bits.
31 30 29
Res. Res. Res. Res.
15 14 13
RTCEN Res. Res. Res.
rw
Bits 31:26 Reserved, must be kept at reset value.
Bit 25 LSCOSEL: Low-speed clock output selection
This bit is set and cleared by software.
0: LSI clock selected
1: LSE clock selected
Bit 24 LSCOEN: Low-speed clock output enable
This bit is set and cleared by software.
0: LSCO disabled
1: LSCO enabled
Bits 23:17 Reserved, must be kept at reset value.
Bit 16 BDRST: Backup domain software reset
This bit is set and cleared by software.
0: Reset not activated
1: Entire Backup domain reset
Bit 15 RTCEN: RTC kernel clock enable
This bit is set and cleared by software. The RTC APB bus clock is controlled by the
RTCAPBEN bit in the RCC_APB1ENR1 and RCC_C2APB1ENR1 registers and the
RTCAPBSMEN bit in the RCC_CnAPB1SMENR1and RCC_C2APB1SMENR1 registers.
0: RTC kernel clock disabled
1: RTC kernel clock enabled
Bits 14:12 Reserved, must be kept at reset value.
Section 7.1.3: Backup domain
28 27 26 25
LSCO
Res. Res.
SEL
rw
12 11 10 9
LSESY
Res. RTCSEL[1:0]
SRDY
r rw
domain. As a result, after Reset, these bits
CORE
PWR control register 1 (PWR_CR1)
Section 6.1.2: Battery Backup domain
24 23 22
LSCO
Res. Res.
EN
rw
8 7 6
LSE LSE
SYSEN CSSD CSSON
rw rw r
RM0453 Rev 1
Reset and clock control (RCC)
reset). Any internal or external
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
LSE LSE
LSEDRV[1:0]
BYP
rw rw rw rw
must be set
for further
17 16
Res. BDRST
rw
1 0
LSE
LSEON
RDY
r rw
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