Backup Domain Control Register (Rcc_Bdcr) - ST STM32F102 Series Reference Manual

RM0008
6.3.9

Backup domain control register (RCC_BDCR)

Address: 0x20
Reset value: 0x0000 0000, reset by Backup domain Reset.
Access: 0 ≤ wait state ≤ 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.
Note: LSEON, LSEBYP, RTCSEL and RTCEN bits of the
(RCC_BDCR)
protected and the DBP bit in the
these can be modified. Refer to
only reset after a Backup domain Reset (see
internal or external Reset will not have any effect on these bits.
31 30 29
15 14 13
RTC
Reserved
EN
rw Res.
Bits 31:17 Reserved, always read as 0.
Bit 16 BDRST Backup domain software reset
Set and reset by software.
0: Reset not activated
1: Resets the entire Backup domain
Bit 15 RTCEN RTC clock enable
Set and reset by software.
0: RTC clock disabled
1: RTC clock enabled
Bits 14:10 Reserved, always read as 0.
Bits 9:8 RTCSEL[1:0] RTC clock source selection
Set by software to select the clock source for the RTC. Once the RTC clock source has been
selected, it cannot be changed anymore unless the Backup domain is reset. The BDRST bit can be
used to reset them.
00: No clock
01: LSE oscillator clock used as RTC clock
10: LSI oscillator clock used as RTC clock
11: HSE oscillator clock divided by 128 used as RTC clock
Bits 7:3 Reserved, always read as 0.
are in the Backup domain. As a result, after Reset, these bits are write-
28 27 26 25
12 11 10 9
RTCSEL[1:0]
rw
Backup domain control register
Power control register (PWR_CR)
Section 5 on page 61
Section 6.1.3: Backup domain
24 23 22
Reserved
Res.
8 7 6
Reserved
rw
Reset and clock control (RCC)
has to be set before
for further information. These bits are
21 20 19 18
5 4 3 2
LSE
BYP
Res. rw
reset). Any
17 16
BDRST
rw
1 0
LSE
LSEON
RDY
r rw
93/690