Flash Control Register (Flash_Cr) - ST STM32WL55JC Reference Manual

RM0453
Bits 9:3 PNB[6:0]: page number selection
Bit 2 MER: mass erase
Bit 1 PER: page erase
Bit 0 PG: programming
4.10.7 FLASH ECC register (FLASH_ECCR)
Address offset: 0x018
Reset value: 0x0000 0000
Access: no wait state when no Flash memory operation is ongoing. Word, half-word and
byte access.
31 30 29 28
ECCD ECCC Res.
rc_w1 rc_w1 r
15 14 13 12
r r r r
Bit 31 ECCD: ECC detection
Bit 30 ECCC: ECC correction
Bit 29 Reserved, must be kept at reset value.
Bits 28:26 CPUID[2:0]: CPU identification
Bit 25 Reserved, must be kept at reset value.
Bit 24 ECCCIE: ECC correction interrupt enable
These bits select the 2-Kbyte page to erase.
0x00: page 0
0x01: page 1
...
0x7F: page 127
When set, this bit triggers the mass erase (all user pages).
0: page erase disabled
1: page erase enabled
0: Flash programming disabled
1: Flash programming enabled
27 26 25
CPUID[2:0] Res. ECCCIE
r r
11 10 9
r r r
Set by hardware when two ECC errors have been detected. When this bit is set, a NMI is
generated.
This bit is cleared by writing 1.
Set by hardware when one ECC error has been detected and corrected. An interrupt is
generated if ECCIE is set.
This bit is cleared by writing 1.
Set by hardware. This bit indicates the Bus-ID of the CPU access causing the ECC failure.
000: CPUID for CPU1 bus ID value
001: CPUID for CPU2 bus ID value
0: ECCC interrupt disabled
1: ECCC interrupt enabled
24 23 22 21
Res. Res. Res.
rw
8 7 6 5
ADDR_ECC[15:0]
r r r r
RM0453 Rev 2
Embedded Flash memory (FLASH)
20 19 18
SYSF_ECC Res. Res. Res.
r
4 3 2
r r r
17 16
ADDR_ECC[16]
r
1 0
r r
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