Flash Control Register (Flash_Cr) - ST STM32G0 1 Series Reference Manual

Embedded Flash memory (FLASH)
3.7.5

FLASH control register (FLASH_CR)

Address offset: 0x014
Reset value: 0xC000 0000
Access: no wait state when no Flash memory operation is on going, word, half-word and
byte access
This register cannot be modified when CFGBSY in
set.
31 30 29 28
OPT SEC_ SEC_
LOCK
LOCK PROT2 PROT
rs rs rw rw
15 14 13 12
MER2 Res. BKER
rw rw rw
Bit 31 LOCK: FLASH_CR Lock
Bit 30 OPTLOCK: Options Lock
Bit 29 SEC_PROT2: Securable memory area protection enable, Bank 2
Bit 28 SEC_PROT: Securable memory area protection enable (Bank 1)
Bit 27 OBL_LAUNCH: Option byte load launch
Bit 26 RDERRIE: PCROP read error interrupt enable
104/1390
27 26 25
OBL_ RD
ERRIE
LAUNCH ERRIE
rc_w1 rw rw
11 10
rw rw rw
This bit is set only. When set, the FLASH_CR register is locked. It is cleared by hardware
after detecting the unlock sequence.
In case of an unsuccessful unlock operation, this bit remains set until the next system reset.
This bit is set only. When set, all bits concerning user option in FLASH_CR register and so
option page are locked. This bit is cleared by hardware after detecting the unlock sequence.
The LOCK bit must be cleared before doing the unlock sequence for OPTLOCK bit.
In case of an unsuccessful unlock operation, this bit remains set until the next reset.
This bit enables the protection on securable area in Bank 2, provided that a non-null
securable memory area size (SEC_SIZE2[7:0]) is defined in option bytes.
0: Disable (securable area accessible)
1: Enable (securable area not accessible)
This bit is possible to set only by software and to clear only through a system reset.
This bit enables the protection on securable area (in Bank 1 for dual-bank devices), provided
that a non-null securable memory area size (SEC_SIZE[7:0]) is defined in option bytes.
0: Disable (securable area accessible)
1: Enable (securable area not accessible)
This bit is possible to set only by software and to clear only through a system reset.
When set, this bit triggers the load of option bytes into option registers. It is automatically
cleared upon the completion of the load. The high state of the bit indicates pending option
byte load.
The bit cannot be cleared by software. It cannot be written as long as OPTLOCK is set.
This bit enables the interrupt generation upon setting the RDERR flag in the FLASH_SR
register.
0: Disable
1: Enable
FLASH status register (FLASH_SR)
24 23 22
EOPIE Res. Res.
rw
9 8 7 6
PNB[9:0]
rw rw rw
RM0444 Rev 5
21 20 19 18
Res. Res. Res. FSTPG
rw
5 4 3 2
MER1
rw rw rw rw
RM0444
is
17 16
OPT
STRT
STRT
rs rs
1 0
PER PG
rw rw