Flash Control Register (Flash_Cr) - ST STM32F410 Reference Manual

Embedded Flash memory interface
Bits 3:2 Reserved, must be kept cleared.
Bit 1 OPERR: Operation error
Bit 0 EOP: End of operation
3.8.5

Flash control register (FLASH_CR)

The Flash control register is used to configure and start Flash memory operations.
Address offset: 0x10
Reset value: 0x8000 0000
Access: no wait state when no Flash memory operation is ongoing, word, half-word and
byte access.
31 30 29 28
LOCK Res. Res. Res.
rs
15 14 13 12
Res. Res. Res. Res.
Bit 31 LOCK: Lock
Bits 30:26 Reserved, must be kept cleared.
Bit 25 ERRIE: Error interrupt enable
Bit 24 EOPIE: End of operation interrupt enable
Bits 23:17 Reserved, must be kept cleared.
Bit 16 STRT: Start
This bit triggers an erase operation when set. It is set only by software and cleared when the
BSY bit is cleared.
Bits 15:10 Reserved, must be kept cleared.
64/771
Set by hardware when a flash operation (programming / erase /read) request is detected and
can not be run because of parallelism, alignment, or write protection error. This bit is set only
if error interrupts are enabled (ERRIE = 1).
Set by hardware when one or more Flash memory operations (program/erase) has/have
completed successfully. It is set only if the end of operation interrupts are enabled (EOPIE =
1).
Cleared by writing a 1.
27 26 25
Res. Res. ERRIE
rw
11 10 9
Res. Res. PSIZE[1:0]
rw
Write to 1 only. When it is set, this bit indicates that the FLASH_CR register is locked. It is
cleared by hardware after detecting the unlock sequence.
In the event of an unsuccessful unlock operation, this bit remains set until the next reset.
This bit enables the interrupt generation when the OPERR bit in the FLASH_SR register is
set to 1.
0: Error interrupt generation disabled
1: Error interrupt generation enabled
This bit enables the interrupt generation when the EOP bit in the FLASH_SR register goes
to 1.
0: Interrupt generation disabled
1: Interrupt generation enabled
24 23 22
EOPIE Res. Res. Res.
rw
8 7 6
Res.
rw rw
RM0401 Rev 3
21 20 19 18
Res. Res. Res.
5 4 3 2
SNB[3:0] MER
rw rw rw rw
RM0401
17 16
Res. STRT
rs
1 0
SER PG
rw rw