Module Operation In Low Power Modes - NXP Semiconductors freescale KV4 Series Reference Manual

Module Operation in Low Power Modes

Table 7-1. Chip power modes (continued)
Chip mode Description
VLPR (Very Low On-chip voltage regulator is in a low power mode that supplies only
Power Run) enough power to run the chip at a reduced frequency. Reduced
frequency Flash access mode (1 MHz); LVD off; internal oscillator
provides a low power 4 MHz source for the core, the bus and the
peripheral clocks.
VLPW (Very Same as VLPR but with the core in sleep mode to further reduce
Low Power power; NVIC remains sensitive to interrupts (FCLK = ON). On-chip
Wait) -via WFI voltage regulator is in a low power mode that supplies only enough
power to run the chip at a reduced frequency.
VLPS (Very Low Places chip in static state with LVD operation off. Lowest power mode
Power Stop)-via with ADC and pin interrupts functional. Peripheral clocks are stopped,
WFI but LPTimer, CMP can be used. NVIC is disabled (FCLK = OFF);
AWIC is used to wake up from interrupt. On-chip voltage regulator is in
a low power mode that supplies only enough power to run the chip at a
reduced frequency. All SRAM is operating (content retained and I/O
states held).
VLLS3 (Very Most peripherals are disabled (with clocks stopped), but LLWU,
Low Leakage LPTimer, CMP can be used. NVIC is disabled; LLWU is used to wake
Stop3) up.
SRAM_U and SRAM_L remain powered on (content retained and I/O
states held).
VLLS2 (Very Most peripherals are disabled (with clocks stopped), but LLWU,
Low Leakage LPTimer, CMP can be used. NVIC is disabled; LLWU is used to wake
Stop2) up.
SRAM_L is powered off. A portion of SRAM_U remains powered on
(content retained and I/O states held).
VLLS1 (Very Most peripherals are disabled (with clocks stopped), but LLWU,
Low Leakage LPTimer, CMP can be used. NVIC is disabled; LLWU is used to wake
Stop1) up.
All of SRAM_U and SRAM_L are powered off. The 32-byte system
register file remain powered for customer-critical data.
VLLS0 (Very Most peripherals are disabled (with clocks stopped), but LLWU can be
Low Leakage used. NVIC is disabled; LLWU is used to wake up
Stop0)
1. Follows the reset flow with the LLWU interrupt flag set for the NVIC.
7.4 Module Operation in Low Power Modes
The following table illustrates the functionality of each module while the chip is in each
of the low power modes. (Debug modules are discussed separately; see
Power Modes.) Number ratings (such as 2 MHz and 1 Mbps) represent the maximum
frequencies or maximum data rates per mode. Also, these terms are used:
110
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Core mode Normal
recovery
method
Run -
Sleep Interrupt
Sleep Deep Interrupt
Sleep Deep Wakeup Reset
Sleep Deep Wakeup Reset
Sleep Deep Wakeup Reset
Sleep Deep Wakeup Reset
Debug in Low
Freescale Semiconductor, Inc.
1
1
1
1