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Field
When addressed as a slave, SRW indicates the value of the R/W command bit of the calling address sent
to the master.
0
Slave receive, master writing to slave
1
Slave transmit, master reading from slave
1
Interrupt Flag
IICIF
This bit sets when an interrupt is pending. This bit must be cleared by software by writing 1 to it, such as in
the interrupt routine. One of the following events can set this bit:
• One byte transfer, including ACK/NACK bit, completes if FACK is 0. An ACK or NACK is sent on the
bus by writing 0 or 1 to TXAK after this bit is set in receive mode.
• One byte transfer, excluding ACK/NACK bit, completes if FACK is 1.
• Match of slave address to calling address including primary slave address, range slave address,
alert response address, second slave address, or general call address.
• Arbitration lost
• In SMBus mode, any timeouts except SCL and SDA high timeouts
• I2C bus stop or start detection if the SSIE bit in the Input Glitch Filter register is 1
0
No interrupt pending
1
Interrupt pending
0
Receive Acknowledge
RXAK
0
Acknowledge signal was received after the completion of one byte of data transmission on the bus
1
No acknowledge signal detected
45.4.5 I2C Data I/O register (I2C_D)
Address: 4006_6000h base + 4h offset = 4006_6004h
Bit
7
Read
Write
Reset
0
Field
DATA
Data
In master transmit mode, when data is written to this register, a data transfer is initiated. The most
significant bit is sent first. In master receive mode, reading this register initiates receiving of the next byte
of data.
NOTE: When making the transition out of master receive mode, switch the I2C mode before reading the
Data register to prevent an inadvertent initiation of a master receive data transfer.
In slave mode, the same functions are available after an address match occurs.
Freescale Semiconductor, Inc.
I2C_S field descriptions (continued)
NOTE:
To clear the I2C bus stop or start detection interrupt: In the interrupt service
routine, first clear the STOPF or STARTF bit in the Input Glitch Filter register by
writing 1 to it, and then clear the IICIF bit. If this sequence is reversed, the IICIF
bit is asserted again.
6
5
0
0
I2C_D field descriptions
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Chapter 45 Inter-Integrated Circuit (I2C)
Description
4
3
2
DATA
0
0
0
Description
1
0
0
0
1239
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