Chapter 45 Inter-Integrated Circuit (I2C); Chip-Specific I2C Information - NXP Semiconductors freescale KV4 Series Reference Manual

Chapter 45
Inter-Integrated Circuit (I2C)
45.1

Chip-specific I2C information

45.1.1 I2C signals
Signal
Transmission complete Output
45.2 Introduction
The inter-integrated circuit (I
communication between a number of devices.
The interface is designed to operate up to 100 kbit/s with maximum bus loading and
timing. The I2C device is capable of operating at higher baud rates, up to a maximum of
clock/20, with reduced bus loading. The maximum communication length and the
number of devices that can be connected are limited by a maximum bus capacitance of
400 pF. The I2C module also complies with the System Management Bus (SMBus)
Specification, version 2.
45.2.1 Features
The I2C module has the following features:
• Compatible with The I
• Multimaster operation
• Software programmable for one of 64 different serial clock frequencies
• Software-selectable acknowledge bit
Freescale Semiconductor, Inc.
I/O
DMA_MUX source 22
2
C, I2C, or IIC) module provides a method of
2
C-Bus Specification
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Connected to
1231