Clock Definitions - NXP Semiconductors freescale KV4 Series Reference Manual

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High-level device clocking diagram
Muliplexers
Dividers
Clock gates
4 MHz IRC
32 kHz IRC
PLL
PRDIV
System oscillator
EXTAL
XTAL_CLK
OSC
XTAL
logic
CG — Clock gate
Note: See subsequent sections for details on where these clocks are used.

6.2.1 Clock definitions

The following table describes the clocks in the previous block diagram.
Clock name
CPU clock / System clock
96
OSC
MCG_Cx
OSC_CR
MCG
FCRDIV
FLL
FRDIV
MCGPLL2XCLK
OSCCLK
CG
DIV
OSC32KCLK
Figure 6-1. Clocking diagram
Table continues on the next page...
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
MCG
MCG_Cx
MCG_Cx
MCG_C1
SIM
CG
MCGFFCLK
OUTDIV1
MCGOUTCLK
OUTDIV2
MCGFLLCLK
MCGPLLCLK
OUTDIV4
PMC
PMC logic
Description
MCGOUTCLK divided by OUTDIV1 clocks the ARM Cortex-
M4 core, RAM, DMA, GPIO, FMC module, and crossbar
switch bus masters.
SIM
SIM_SOPT1, SIM_SOPT2
SIM_CLKDIVx
SIM_SCGCx
Clock options for
MCGIRCLK
some peripherals
(see note)
system (CPU) clock
CG
fast peripheral clock
CG
Bus /Flash clock
CG
nano-edge2x clock
OSCERCLK_UNDIV
OSCERCLK
ERCLK32K
LPO
Freescale Semiconductor, Inc.

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