Output Compare Mode - NXP Semiconductors freescale KV4 Series Reference Manual

Table of Contents

Functional description

system clock

channel (n) input

Channel (n) input after its synchronizer and filter

MOD = 0xFFFF

CNTIN = 0x0000

PS[2:0] = 3'b000

ICRST = 1'b1

Figure 39-179. Example of the Input Capture mode with ICRST = 1

• It is expected that the ICRST bit be set only when the channel is in input capture

• In this case, if the FTM counter is reset, then the prescaler counter (Prescaler) and the

(When the TOF bit is

39.5.5 Output Compare mode

The Output Compare mode is selected when:

• DECAPEN = 0

• COMBINE = 0

• CPWMS = 0, and

• MSnB:MSnA = 0:1

In Output Compare mode, the FTM can generate timed pulses with programmable

position, polarity, duration, and frequency. When the counter matches the value in the

CnV register of an output compare channel, the channel (n) output can be set, cleared, or

When a channel is initially configured to Toggle mode, the previous value of the channel

output is held until the first output compare event occurs.

The CHnF bit is set and the channel (n) interrupt is generated if CHnIE = 1 at the channel

(n) match (FTM counter = CnV).

set) also are reset.

KV4x Reference Manual, Rev. 2, 02/2015

0x00 0x01 0x02 0x03

selected channel (n) input event: rising edge

Freescale Semiconductor, Inc.