Clock Divider Values After Reset - NXP Semiconductors freescale KV4 Series Reference Manual

Internal clocking requirements
To enable nanoedge module for nanosecond resolution,
PLL must be enabled to provide high frequencies clock
source, MCGPLLCLK and MCGPLL2XCLK. When
nanoedge enable, system clock source(core and system
clock, fast bus clock, slow bus and flash clock must be
from/divided from MCGPLLCLK.
The following are a few of the more common clock configurations for this device:
High Speed Run Mode
System (CPU) clock
Fast Peripheral clock
Bus / Flash clock
High speed Run mode
System (CPU) clock
Fast Peripheral clock
Bus / Flash clock
RUN mode
System (CPU) clock
Fast Peripheral clock
Bus / Flash clock
RUN mode
System (CPU) clock
Fast Peripheral clock
Bus / Flash clock

6.3.1 Clock divider values after reset

Each clock divider is programmed via the SIM module's CLKDIVn registers. The flash
memory's FTFA_FOPT[LPBOOT] bit controls the reset value of the core clock, system
clock, bus clock, and flash clock dividers as shown below:+
98
NOTE
150 MHz max.
75 MHz max.
25 MHz max
120 MHz
120 MHz
24 MHz
100 MHz
100 MHZ
25 MHz max
50 MHz
100 MHz
25 MHz max
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Frequency
Frequency
Frequency
Frequency
Freescale Semiconductor, Inc.