Dual Edge Capture Mode - NXP Semiconductors freescale KV4 Series Reference Manual

Functional description
Table 39-252. Channel DMA transfer request (continued)
DMA CHnIE Channel DMA Transfer Request
1 1 The channel DMA transfer request is generated if
(CHnF = 1).
If DMA = 1, the CHnF bit is cleared either by channel DMA transfer done or reading
CnSC while CHnF is set and then writing a zero to CHnF bit according to CHnIE bit. See
the following table.
CHnIE How CHnF Bit Can Be Cleared
0 CHnF bit is cleared either when the channel DMA transfer is done or by reading CnSC while CHnF is set and
then writing a 0 to CHnF bit.
1 CHnF bit is cleared when the channel DMA transfer is done.

39.5.24 Dual Edge Capture mode

The Dual Edge Capture mode is selected if DECAPEN = 1. This mode allows to measure
a pulse width or period of the signal on the input of channel (n) of a channel pair. The
channel (n) filter can be active in this mode when n is 0 or 2.
synchronizer
channel (n) input
D
system clock
CLK
* Filtering function for dual edge capture mode is only available in the channels 0 and 2
Figure 39-247. Dual Edge Capture mode block diagram
The MS(n)A bit defines if the Dual Edge Capture mode is one-shot or continuous.
1006
Table 39-253. Clear CHnF bit when DMA = 1
Q D Q
Filter*
CLK
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Channel Interrupt
The channel interrupt is not generated.
FTMEN
DECAPEN
is filter
DECAP
enabled?
MS(n)A
ELS(n)B:ELS(n)A
ELS(n+1)B:ELS(n+1)A
0
Dual edge capture
mode logic
1
FTM counter
channel (n)
interrupt
CH(n)IE
CH(n)F
C(n)V[15:0]
channel (n+1)
CH(n+1)IE interrupt
CH(n+1)F
C(n+1)V[15:0]
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