Espressif ESP32 Technical Reference Manual page 519

18 Timer Group (TIMG)
31
TIMGn_RTC_CALI_VALUE Calibration value when cycles of clock to be calibrated reach
TIMGn_RTC_CALI_MAX, in unit of XTAL_CLK clock cycles. (RO)
31
0 0 0 0 0 0 0
TIMGn_INT_WDT_INT_ENA The interrupt enable bit for the
(R/W)
TIMGn_INT_T1_INT_ENA The interrupt enable bit for the
TIMGn_INT_T0_INT_ENA The interrupt enable bit for the
31
0 0 0 0 0 0 0
TIMGn_INT_WDT_INT_RAW The raw interrupt status bit for the
TIMGn_INT_T1_INT_RAW The raw interrupt status bit for the
TIMGn_INT_T0_INT_RAW The raw interrupt status bit for the
Espressif Systems
Register 18.19. TIMGn_RTCCALICFG1_REG (0x006C)
0x00000
Register 18.20. TIMGn_INT_ENA_REG (0x0098)
0 0 0 0 0 0 0 0
Register 18.21. TIMGn_INT_RAW_REG (0x009c)
0 0 0 0 0 0 0 0
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0 0 0 0 0 0 0 0
TIMGn_INT_WDT_INT
TIMGn_INT_T1_INT
TIMGn_INT_T0_INT
0 0 0 0 0 0 0 0
TIMGn_INT_WDT_INT
TIMGn_INT_T1_INT
TIMGn_INT_T0_INT
519
7 5 0
0 0 0 0 0 0
3 2 1
0 0 0 0 0 0 0 0
interrupt. (R/W)
interrupt. (R/W) (R/W)
interrupt. (R/W) (R/W)
3 2 1
0 0 0 0 0 0 0 0
interrupt. (RO)
interrupt. (RO)
interrupt. (RO)
ESP32 TRM (Version 5.2)
Reset
0
0
Reset
0
0 Reset