Espressif ESP32 Technical Reference Manual page 293

11 I2C Controller (I2C)
11.3.5 I2C Master Writes to Slave
Figure 11-5. I2C Master Writes to Slave with 7-bit Address
In all subsequent figures that illustrate I2C transactions and behavior, both the I2C Master and Slave devices
are assumed to be ESP32 I2C peripheral controllers for ease of demonstration.
Figure 11-5 shows the I2C Master writing N bytes of data to an I2C Slave. According to the I2C protocol, the first
byte is the Slave address. As shown in the diagram, the first byte of the RAM unit has been populated with the
Slave's 7-bit address plus the 1-bit read/write flag. In this case, the flag is zero, indicating a write operation. The
rest of the RAM unit holds N bytes of data ready for transmission. The cmd unit has been populated with the
sequence of commands for the operation.
For the I2C master to begin an operation, the bus must not be busy, i.e. the SCL line must not be pulled low
by another device on the I2C bus. The I2C operation can only begin when the SCL line is released (made
high) to indicate that the I2C bus is free. After the cmd unit and data are prepared, I2C_TRANS_START bit in
I2C_CTR_REG must be set to begin the configured I2C Master operation. The I2C Master then initiates a START
condition on the bus and progresses to the WRITE command which will fetch N+1 bytes from RAM and send
them to the Slave. The first of these bytes is the address byte.
When the transmitted data size exceeds I2C_NONFIFO_TX_THRES, an I2C_TX_SEND_EMPTY_INT interrupt will
be generated. After detecting the interrupt, software can read TXFIFO_END_ADDR in register RXFIFO_ST_REG,
get the last address of the data in the RAM and refresh the old data in the RAM. TXFIFO_END_ADDR will be
refreshed each time interrupt I2C_TX_SEND_EMPTY_INT or I2C_TRANS_COMPLETE_INT occurs.
When ack_check_en is set to 1, the Master will check the ACK value each time it sends a data byte. If the ACK
value received does not match ack_exp (the expected ACK value) in the WRITE command, then the Master will
generate an I2C_ACK_ERR_INT interrupt and stop the transmission.
During transmission, when the SCL is high, if the input value and output value of SDA do not match, then the
Master will generate an I2C_ARBITRATION_LOST_INT interrupt. When the transmission is finished, the Master
will generate an I2C_TRANS_COMPLETE_INT interrupt.
After detecting the START bit sent from the Master, the Slave will start receiving the address and comparing it
to its own. If the address does not match I2C_SLAVE_ADDR, then the Slave will ignore the rest of the trans-
mission. If they do match, the Slave will store the rest of the data into RAM in the receiving order. When the
data size exceeds I2C_NONFIFO_RX_THRES, an I2C_RX_REC_FULL_INT interrupt is generated. After detecting
Espressif Systems 293 ESP32 TRM (Version 5.2)
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