31 Low-Power Management (RTC_CNTL)
31
0
0
0
0
0
0
0
RTC_CNTL_MAIN_TIMER_INT_ENA The interrupt enable bit for the RTC_CNTL_MAIN_TIMER_INT
interrupt. (R/W)
RTC_CNTL_BROWN_OUT_INT_ENA The interrupt enable bit for the
RTC_CNTL_BROWN_OUT_INT interrupt. (R/W)
RTC_CNTL_TOUCH_INT_ENA The interrupt enable bit for the RTC_CNTL_TOUCH_INT interrupt.
(R/W)
RTC_CNTL_ULP_CP_INT_ENA The interrupt enable bit for the RTC_CNTL_ULP_CP_INT interrupt.
(R/W)
RTC_CNTL_TIME_VALID_INT_ENA The interrupt enable bit for the RTC_CNTL_TIME_VALID_INT in-
terrupt. (R/W)
RTC_CNTL_WDT_INT_ENA The interrupt enable bit for the RTC_CNTL_WDT_INT interrupt. (R/W)
RTC_CNTL_SDIO_IDLE_INT_ENA The interrupt enable bit for the RTC_CNTL_SDIO_IDLE_INT inter-
rupt. (R/W)
RTC_CNTL_SLP_REJECT_INT_ENA The interrupt enable bit for the RTC_CNTL_SLP_REJECT_INT in-
terrupt. (R/W)
RTC_CNTL_SLP_WAKEUP_INT_ENA The interrupt enable bit for the
RTC_CNTL_SLP_WAKEUP_INT interrupt. (R/W)
Espressif Systems
Register 31.14. RTC_CNTL_INT_ENA_REG (0x003C)
0
0
0
0
0
0
0
0
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9
8
0
0
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0
0
0
0
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0
712
7
6
5
4
3
2
1
0
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Reset
ESP32 TRM (Version 5.2)
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