Espressif ESP32 Technical Reference Manual page 28

1 System and Memory
Bus Type
Low Address
Data 0x3FF8_0000
0x3FF8_2000
Data 0x3FF9_0000
0x3FFA_0000
Data 0x3FFA_E000
Data 0x3FFE_0000
Bus Type
Low Address
Instruction 0x4000_0000
Instruction 0x4000_8000
0x4006_0000
Instruction 0x4007_0000
Instruction 0x4008_0000
Instruction 0x400A_0000
Instruction 0x400B_0000
Instruction 0x400B_8000
Instruction 0x400C_0000
Bus Type
Low Address
Data Instruc-
0x5000_0000
tion
1.3.2.1 Internal ROM 0
The capacity of Internal ROM 0 is 384 KB. It is accessible by both CPUs through the address range 0x4000_0000
~ 0x4005_FFFF, which is on the instruction bus.
The address range of the first 32 KB of the ROM 0 (0x4000_0000 ~ 0x4000_7FFF) can be remapped in order
to access a part of Internal SRAM 1 that normally resides in a memory range of 0x400B_0000 ~ 0x400B_7FFF.
While remapping, the 32 KB SRAM cannot be accessed by an address range of 0x400B_0000 ~ 0x400B_7FFF
any more, but it can still be accessible through the data bus (0x3FFE_8000 ~ 0x3FFE_FFFF). This can be done
on a per-CPU basis: setting bit 0 of register DPORT_PRO_BOOT_REMAP_CTRL_REG or DPORT_APP_BOOT_REMAP_CTRL_REG
will remap SRAM for the PRO_CPU and APP_CPU, respectively.
1.3.2.2 Internal ROM 1
The capacity of Internal ROM 1 is 64 KB. It can be read by either CPU at an address range 0x3FF9_0000 ~
0x3FF9_FFFF of the data bus.
1.3.2.3 Internal SRAM 0
The capacity of Internal SRAM 0 is 192 KB. Hardware can be configured to use the first 64 KB to cache external
memory access. When not used as cache, the first 64 KB can be read and written by either CPU at addresses
Espressif Systems
Table 1-2. Embedded Memory Address Mapping
Boundary Address
High Address
0x3FF8_1FFF
0x3FF8_FFFF
0x3FF9_FFFF
0x3FFA_DFFF
0x3FFD_FFFF
0x3FFF_FFFF
Boundary Address
High Address
0x4000_7FFF
0x4005_FFFF
0x4006_FFFF
0x4007_FFFF
0x4009_FFFF
0x400A_FFFF
0x400B_7FFF
0x400B_FFFF
0x400C_1FFF
Boundary Address
High Address
0x5000_1FFF
Submit Documentation Feedback
Size Target
8 KB RTC FAST Memory
56 KB Reserved
64 KB Internal ROM 1
56 KB Reserved
200 KB Internal SRAM 2
128 KB Internal SRAM 1
Size Target
32 KB Internal ROM 0
352 KB Internal ROM 0
64 KB Reserved
64 KB Internal SRAM 0
128 KB Internal SRAM 0
64 KB Internal SRAM 1
32 KB Internal SRAM 1
32 KB Internal SRAM 1
8 KB RTC FAST Memory
Size Target
8 KB RTC SLOW Memory
28
Comment
PRO_CPU Only
-
-
-
DMA
DMA
Comment
Remap
-
-
Cache
-
-
Remap
-
PRO_CPU Only
Comment
-
ESP32 TRM (Version 5.2)