Espressif ESP32 Technical Reference Manual page 652

29 On-Chip Sensors and Analog Signal Processing
31
0 0 0 0 0 0 0
SENS_SAR1_STOP Stop SAR ADC1 conversion. (R/W)
SENS_SAR2_STOP Stop SAR ADC2 conversion. (R/W)
SENS_PC_INIT Initialized PC for ULP coprocessor. (R/W)
SENS_ULP_CP_START_TOP Write 1 to start ULP coprocessor;
reg_ulp_cp_force_start_top = 1. (R/W)
SENS_ULP_CP_FORCE_START_TOP 1: ULP coprocessor is started by SW, 0: ULP coprocessor is
started by timer. (R/W)
SENS_SAR2_PWDET_CCT SAR2_PWDET_CCT, PA power detector capacitance tuning. (R/W)
SENS_SAR2_EN_TEST SAR2_EN_TEST is active only when reg_sar2_dig_force = 0. (R/W)
SENS_SAR2_BIT_WIDTH Bit width of SAR ADC2, 00: 9 bits, 01: 10 bits, 10: 11 bits, 11: 12 bits. (R/W)
SENS_SAR1_BIT_WIDTH Bit width of SAR ADC1, 00: 9 bits, 01: 10 bits, 10: 11 bits, 11: 12 bits. (R/W)
31
SENS_SAR_ATTEN1_REG 2-bit attenuation for each pad, 11: 1 dB, 10: 6 dB, 01: 3 dB, 00: 0 dB, [1:0]
is used for ADC1_CH0, [3:2] is used for ADC1_CH1, etc. (R/W)
31
SENS_SAR_ATTEN2_REG 2-bit attenuation for each pad, 11: 1 dB, 10: 6 dB, 01: 3 dB, 00: 0 dB,
[1:0] is used for ADC2_CH0, [3:2] is used for ADC2_CH1, etc (R/W)
Espressif Systems
Register 29.3. SENS_SAR_START_FORCE_REG (0x002c)
24 23 22 21
0 0 0 0 0 0 0 0
Register 29.4. SENS_SAR_ATTEN1_REG (0x0034)
0x0FFFFFFFF
Register 29.5. SENS_SAR_ATTEN2_REG (0x0038)
0x0FFFFFFFF
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11 10 9
0 0 0 0 0 0 0 0
652
8 7 5 4 3 2 1
0 0 0 0 0 1 1 1
it is active only when
ESP32 TRM (Version 5.2)
0
1 Reset
0
Reset
0
Reset