Espressif ESP32 Technical Reference Manual page 613

27 Memory Management and Protection Units (MMU, MPU)
Size
Low
8 KB 0x3FF8_0000
8 KB 0x400C_0000
Boundary address
Size
Low
8 KB 0x5000_0000 0x5000_1FFF Read/Write
Register RTC_CNTL_RTC_PID_CONFIG_REG is part of the RTC peripheral and can only be modified by processes
with a PID of 0; register DPORT_AHBLITE_MPU_TABLE_RTC_REG is a Dport register and can be changed by
processes with a PID of 0 or 1.
SRAM0 and SRAM2 upper 128 KB MMUs
Both the upper 128 KB of SRAM0 and the upper 128 KB of SRAM2 are governed by an MMU. Not only can these
MMUs allow or deny access to the memory they govern (just like the MPUs do), but they are also capable of
translating the address a CPU reads from or writes to (which is a virtual address) to a possibly different address
in memory (the physical address).
In order to accomplish this, the internal RAM MMUs divide the memory range they govern into 16 pages. The
page size is configurable as 8 KB, 4 KB and 2 KB. When the page size is 8 KB, the 16 pages span the entire 128
KB memory region; when the page size is 4 KB or 2 KB, a non-MMU-covered region of 64 or 96 KB, respectively,
will exist at the end of the memory space. Similar to the virtual and physical addresses, it is also possible to
imagine the pages as having a virtual and physical component. The MMU can convert an address within a virtual
page to an address within a physical page.
For PID 0 and 1, this mapping is 1-to-1, meaning that a read from or write to a certain virtual page will always be
converted to a read from or write to the exact same physical page. This allows an operating system, running
under PID 0 and/or 1, to always have access to the entire physical memory range.
For PID 2 to 7, however, every virtual page can be reconfigured, on a per-PID basis, to map to a different physical
page. This way, reads and writes to an offset within a virtual page get translated into reads and writes to the
same offset within a different physical page. This is illustrated in Figure 27-1: the CPU (running a process with
a PID between 2 to 7) tries to access memory address 0x3FFC_2345. This address is within the virtual Page
1 memory region, at offset 0x0345. The MMU is instructed that for this particular PID, it should translate an
access to virtual page 1 into physical Page 2. This causes the memory access to be redirected to the same
offset as the virtual memory access, yet in Page 2, which results in the effective access of physical memory
address 0x3FFC_4345. The page size in this example is 8 KB.
Espressif Systems
Table 27-2. MPU for RTC FAST Memory
Boundary address
High
0x3FF8_1FFF
0x400C_1FFF
Table 27-3. MPU for RTC SLOW Memory
High PID = 0/1
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Authority
RTC_CNTL_RTC_PID_CONFIG bit
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
Authority
DPORT_AHBLITE_MPU_TABLE_RTC_REG bit
613
PID
PID
2 3 4 5 6 7
0 1 2 3 4 5
ESP32 TRM (Version 5.2)