Espressif ESP32 Technical Reference Manual page 380

13 UART Controller (UART)
31
0 0 0 0 0 0 0
UHCI_SEND_A_REG_Q_INT_ST The masked interrupt status bit for the
interrupt. (RO)
UHCI_SEND_S_REG_Q_INT_ST The masked interrupt status bit for the
interrupt. (RO)
UHCI_OUT_TOTAL_EOF_INT_ST The masked interrupt status bit for the
interrupt. (RO)
UHCI_OUTLINK_EOF_ERR_INT_ST The
UHCI_OUTLINK_EOF_ERR_INT
UHCI_IN_DSCR_EMPTY_INT_ST The
UHCI_IN_DSCR_EMPTY_INT
UHCI_OUT_DSCR_ERR_INT_ST The masked interrupt status bit for the
interrupt. (RO)
UHCI_IN_DSCR_ERR_INT_ST The masked interrupt status bit for the
terrupt. (RO)
UHCI_OUT_EOF_INT_ST The masked interrupt status bit for the
UHCI_OUT_DONE_INT_ST The masked interrupt status bit for the
(RO)
UHCI_IN_ERR_EOF_INT_ST The masked interrupt status bit for the
rupt. (RO)
UHCI_IN_SUC_EOF_INT_ST The masked interrupt status bit for the
rupt. (RO)
UHCI_IN_DONE_INT_ST The masked interrupt status bit for the
UHCI_TX_HUNG_INT_ST The masked interrupt status bit for the
UHCI_RX_HUNG_INT_ST The masked interrupt status bit for the
(RO)
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Espressif Systems
Register 13.31. UHCI_INT_ST_REG (0x8)
17
0 0 0 0 0 0 0 0
interrupt. (RO)
masked
interrupt. (RO)
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16 15 14 13 12 11 10 9
0 0 0 0 0 0 0 0
masked interrupt
interrupt
UHCI_OUT_EOF_INT
UHCI_OUT_DONE_INT
UHCI_IN_DONE_INT
UHCI_TX_HUNG_INT
UHCI_RX_HUNG_INT
380
8 7 6 5 4 3 2 1
0 0 0 0 0 0 0 0
UHCI_SEND_A_REG_Q_INT
UHCI_SEND_S_REG_Q_INT
UHCI_OUT_TOTAL_EOF_INT
status bit for
status bit for
UHCI_OUT_DSCR_ERR_INT
UHCI_IN_DSCR_ERR_INT
interrupt. (RO)
interrupt.
UHCI_IN_ERR_EOF_INT
UHCI_IN_SUC_EOF_INT
interrupt. (RO)
interrupt. (RO)
interrupt.
ESP32 TRM (Version 5.2)
0
0 Reset
the
the
in-
inter-
inter-