Espressif ESP32 Technical Reference Manual page 235

10 Ethernet Media Access Controller (MAC)
10.6.1 MII (Media Independent Interface)
Media Independent Interface (MII) defines the interconnection between MAC sublayers and PHYs at the data
transmission rate of 10 Mbit/s and 100 Mbit/s.
10.6.1.1 Interface Signals Between MII and PHY
Interface signals between MII and PHY are shown in Figure 10-3.
MII Interface Signal Description:
• MII_TX_CLK: TX clock signal. This signal provides the reference timing for TX data transmission. The
frequencies are divided into two types: 2.5 MHz at a data transmission rate of 10 Mbit/s, and 25 MHz at
100 Mbit/s.
• MII_TXD[3:0]: Transmit data signal in groups of four, syn-driven by the MAC sub-layer, and valid only
when the MII_TX_EN signal is valid. MII_TXD[0] is the lowest significant bit and MII_TXD[3] is the highest
significant bit. When the signal MII_TX_EN is pulled low, sending data does not have any effect on the
PHY.
• MII_TX_EN: Transmit data enable signal. This signal indicates that the MAC is currently sending nibbles
(4 bits) for the MII. This signal must be synchronized with the first nibble of the header (MII_TX_CLK) and
must be synchronized when all nibbles to be transmitted are sent to the MII.
• MII_RX_CLK: RX clock signal. This signal provides the reference timing for RX data transmission. The
frequencies are divided into two types: 2.5 MHz at the data transmission rate of 10 Mbit/s, and 25 MHz
at 100 Mbit/s.
• MII_RXD[3:0]: Receive data signal in groups of four, syn-driven by the PHY, and valid only when MII_RX_DV
signal is valid. MII_RXD[0] is the lowest significant bit and MII_RXD[3] is the highest significant bit. When
MII_RX_DV is disabled and MII_RX_ER is enabled, the specific MII_RXD[3:0] value represents specific
information from the PHY.
• MII_RX_DV: Receive data valid signal. This signal indicates that the PHY is currently receiving the recov-
ered and decoded nibble that will be transmitted to the MII. This signal must be synchronized with the first
nibble of the recovered frame (MII_RX_CLK) and remain synchronized till the last nibble of the recovered
Espressif Systems
Figure 10-3. MII Interface
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