Espressif ESP32 Technical Reference Manual page 156

7 SPI Controller (SPI)
31
0 0 0 0 0 0 0
SPI_OUT_TOTAL_EOF_INT_ST The masked interrupt status bit for the
terrupt. (RO)
SPI_OUT_EOF_INT_ST The masked interrupt status bit for the
SPI_OUT_DONE_INT_ST The masked interrupt status bit for the
SPI_IN_SUC_EOF_INT_ST The masked interrupt status bit for the
(RO)
SPI_IN_ERR_EOF_INT_ST The masked interrupt status bit for the
(RO)
SPI_IN_DONE_INT_ST The masked interrupt status bit for the
SPI_INLINK_DSCR_ERROR_INT_ST The
SPI_INLINK_DSCR_ERROR_INT
SPI_OUTLINK_DSCR_ERROR_INT_ST The
SPI_OUTLINK_DSCR_ERROR_INT
SPI_INLINK_DSCR_EMPTY_INT_ST The
SPI_INLINK_DSCR_EMPTY_INT
Espressif Systems
Register 7.31. SPI_DMA_INT_ST_REG (0x118)
0 0 0 0 0 0 0 0
interrupt. (RO)
interrupt. (RO)
interrupt. (RO)
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9
0 0 0 0 0 0 0 0
SPI_OUT_EOF_INT
SPI_OUT_DONE_INT
SPI_IN_SUC_EOF_INT
SPI_IN_ERR_EOF_INT
SPI_IN_DONE_INT
masked interrupt
masked interrupt
masked interrupt
156
8 7 6 5 4 3 2 1
0 0 0 0 0 0 0 0
SPI_OUT_TOTAL_EOF_INT
interrupt. (RO)
interrupt. (RO)
interrupt.
interrupt.
interrupt. (RO)
status bit for
status bit for
status bit for
ESP32 TRM (Version 5.2)
0
0
Reset
in-
the
the
the