Espressif ESP32 Technical Reference Manual page 358

13 UART Controller (UART)
13.5 Registers
13.5.1 UART Registers
The addresses in parenthesis besides register names are the register addresses relative to the UART base
address provided in Table
register addresses are listed in Section
13.5.2 UHCI Registers
31
0 0 0 0 0 0 0
UART_RXFIFO_RD_BYTE
Espressif Systems
1-6 Peripheral Address Mapping in Chapter
13.4.1 UART Register
Register 13.1. UART_FIFO_REG (0x0)
0 0 0 0 0 0 0 0
UARTn accesses FIFO via this register. (R/W)
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1 System and
Summary.
0 0 0 0 0 0 0 0
358
Memory. The absolute
8 7
0 0 0 0 0 0 0 0
ESP32 TRM (Version 5.2)
0
0
Reset