Espressif ESP32 Technical Reference Manual page 286

10 Ethernet Media Access Controller (MAC)
31
0 0 0 0 0 0 0
PWDOGEN When this bit is set and Bit[23] (WD) of EMACCONFIG_REG is reset, the WTO field
(Bits[13:0]) is used as watchdog timeout for a received frame. When this bit is cleared, the
watchdog timeout for a received frame is controlled by the setting of Bit[23] (WD) and Bit[20]
(JE) in EMACCONFIG_REG. (R/W)
WDOGTO When Bit[16] (PWE) is set and Bit[23] (WD) of EMACCONFIG_REG is reset, this field is used
as watchdog timeout for a received frame. If the length of a received frame exceeds the value
of this field, such frame is terminated and declared as an error frame. (R/W)
31
0 0 0 0 0 0 0
EMAC_CLK_OUT_H_DIV_NUM RMII CLK using internal APLL CLK, the half divider number, when
using RMII PHY. (R/W)
EMAC_CLK_OUT_DIV_NUM RMII CLK using internal APLL CLK, the whole divider number, when
using RMII PHY. (R/W)
Espressif Systems
Register 10.43. EMACWDOGTO_REG (0x10DC)
17
0 0 0 0 0 0 0 0
Register 10.44. EMAC_EX_CLKOUT_CONF_REG (0x0800)
0 0 0 0 0 0 0 0
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16 15 14 13
0 0 0
0 0 0 0 0 0 0 0
286
0x0000
8 7 4 3
0 0x02 0x04
ESP32 TRM (Version 5.2)
0
Reset
0
Reset