Espressif ESP32 Technical Reference Manual page 44

3 Reset and Clock
CPU_CLK Source
PLL_CLK
APLL_CLK
XTL_CLK
FOSC_CLK
For example, when CPU_CLK source is PLL_CLK and users need to keep the REF_TICK frequency at 1 MHz,
then they should set SYSCON_PLL_TICK_NUM to 79 (0x4F) so that the REF_TICK frequency = 80 MHz / (79+1)
= 1 MHz.
3.2.4.3 LEDC_SCLK Source
The LEDC_SCLK clock source is selected by the LEDC_APB_CLK_SEL register, as shown in Table 3-7.
3.2.4.4 APLL_SCLK Source
The APLL_CLK is sourced from PLL_CLK, with its output frequency configured using the APLL configuration
registers.
3.2.4.5 PLL_F160M_CLK Source
PLL_F160M_CLK is divided from PLL_CLK by automatically adjusting the clock division and its frequency is
always 160 MHz.
3.2.4.6 Clock Source Considerations
Most peripherals will operate using the APB_CLK frequency as a reference. When this frequency changes, the
peripherals will need to update their clock configuration to operate at the same frequency after the change. Pe-
ripherals accessing REF_TICK can continue operating normally when switching clock sources, without changing
clock source. Please see Table
The LED PWM module can use RC_FAST_CLK as a clock source when APB_CLK is disabled. In other words,
when the system is in low-power consumption mode (see
be halted (APB_CLK is turned off), but the LED PWM can work normally via RC_FAST_CLK.
3.2.5 Wi-Fi BT Clock
Wi-Fi and BT can only operate if APB_CLK uses PLL_CLK as its clock source. Suspending PLL_CLK requires
Wi-Fi and BT to both have entered low-power consumption mode first.
For LOW_POWER_CLK, one of RC_SLOW_CLK, RTC_SLOW_CLK, RC_FAST_CLK or XTL_CLK can be selected as
the low-power consumption mode clock source for Wi-Fi and BT.
Espressif Systems
Table 3-6. REF_TICK
APB_CLK Frequency
80 MHz
CPU_CLK / 2
CPU_CLK
CPU_CLK
Table 3-7. LEDC_SCLK Derivation
LEDC_APB_CLK_SEL Value
0
1
3-4 for details.
44
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REF_TICK Frequency
APB_CLK / (SYSCON_PLL_TICK_NUM+1)
APB_CLK / (SYSCON_APLL_TICK_NUM+1)
APB_CLK / (SYSCON_XTAL_TICK_NUM+1)
APB_CLK / (SYSCON_CK8M_TICK_NUM+1)
LEDC_SCLK Source
RC_FAST_CLK
APB_CLK
Power Management Chapter), normal peripherals will
ESP32 TRM (Version 5.2)